What is Controlled Depth Drilling?

Controlled depth drilling (CDD) is a PCB manufacturing process used to create precise, blind vias and through holes of specific depths in multilayer PCB stackups. By carefully controlling the depth of the drills, controlled depth drilling allows for the creation of complex interconnects between layers without penetrating through the entire board thickness.

CDD offers several advantages over traditional through-hole drilling:

• Enables higher density interconnects by drilling blind vias
• Avoids unnecessary hole stubs on non-connected layers
• Improves signal integrity by minimizing stubs and reflections
• Reduces overall board thickness

The key to successful controlled depth drilling is precisely configuring the layer stackup and specifying the desired drilling depths for each hole. Let’s take a closer look at how to set up controlled depth drilling in a PCB design.

Designing the PCB Stackup for Controlled Depth Drilling

The first step in configuring CDD is carefully planning out the layer stackup of the PCB. The stackup defines the number of copper layers, dielectric material types and thicknesses, and drill spans.

Here is an example 6-layer PCB stackup with controlled depth drilling:

Layer	Material	Thickness (mil)	Drill Span
1 – Top Copper	1 oz Copper	1.4	–
2 – Ground	1 oz Copper	1.4	–
FR-4 Core	FR-4	28	–
3 – Signal	1/2 oz Copper	0.7	Span 1
4 – Signal	1/2 oz Copper	0.7	Span 1
FR-4 Core	FR-4	32	–
5 – Signal	1/2 oz Copper	0.7	Span 2
6 – Bottom Copper	1 oz Copper	1.4	–

In this example, there are two distinct drill spans configured:

• Span 1 drills from the top through layers 1-4 and stops at layer 5
• Span 2 drills from the bottom through layer 6 and stops at layer 5

By using two separate spans, blind vias can be created connecting the outer layers to the inner layers without drilling all the way through. The FR-4 core thicknesses are chosen to provide sufficient depth for mechanical rigidity.

Specifying Drill Spans and Depths

With the basic stackup defined, the next step is to specify the exact drilling depths for each span. This requires careful calculations based on the individual layer thicknesses.

To calculate the drill depths:

1. Add up the total thickness of the dielectric layers and copper layers within each span.
2. Subtract a small depth margin, typically 4-8 mils, to ensure the drill does not inadvertently penetrate the underlying layer.

For example, to calculate the drilling depth for Span 1:

• Top copper (1.4) + Top FR-4 (18) + L3 copper (0.7) + L4 copper (0.7) + Bottom FR-4 (18) = 38.8 mils total
• 38.8 mils – 6 mil depth margin = 32.8 mil drilling depth

So Span 1 would be drilled to a controlled depth of 32.8 mils to safely land on layer 5 without punching through.

Repeat this calculation for each additional drill span in the stackup. Be sure to clearly communicate the layer stackup and drilling depths to the PCB fabricator to ensure accuracy.

Back-drilling Stubs for Improved Signal Integrity

Another technique often used in conjunction with controlled depth drilling is back-drilling unused via stubs. Even with CDD, the drilling process can leave behind short stub remnants on layers where the via is not connected. At high frequencies, these stubs can cause undesired signal reflections and degrade performance.

Back-drilling is a secondary process that removes the unused stub portions of the hole. A specialized back-drilling machine is used to essentially counterbore the hole and remove the stub.

Not all vias require back-drilling – it is typically only needed for high-speed, impedance controlled signals like DDR memory or SerDes channels. The PCB designer must identify which vias are to be back-drilled and call them out in the fabrication drawing.

Here are some general guidelines for when to use back-drilling:

• High-speed signals above ~5 Gbps
• Signals with rise times faster than ~200 ps
• Differential pairs routed through vias
• Vias in BGA escape regions or under chip packages

As a rule of thumb, the maximum stub length to drill out should be less than 20-30% of the signal’s rise time to minimize the impact of reflections. The longer the stub, the worse the signal degradation.

Configuring Back-drilling in the PCB Layout

To set up back-drilling in the PCB layout tool, follow these steps:

1. Create a special via type for the back-drilled vias, with unique properties like drill size, annular ring size, etc.

2. Place the back-drilled vias on the PCB as required for the high-speed nets.

3. On the fabrication drawing layer, manually draw a “B/D” symbol next to each via that requires back-drilling. Call out the specific via name or coordinates.

4. Create the hole size chart and drill table, listing the finished hole size, back-drill hole size, and back-drill depth for each via type.

5. Include a detailed stackup diagram showing the layer thicknesses and materials.

6. Clearly mark the drilling spans, depths, and back-drilling instructions on the fabrication drawing.

Communicating the back-drilling requirements accurately to the manufacturer is critical. Even small stub remnants can significantly impact high-speed signal performance.

Panelization Considerations for Controlled Depth Drilling

When panelizing PCBs that use controlled depth drilling or back-drilling, there are a few additional considerations to keep in mind:

Drilling Accuracy and Registration

Controlled depth drilling and back-drilling require precise alignment between the drilled holes and the target copper layers. Any registration errors can result in inaccurate drilling depths or stubs.

To ensure accuracy, PCB panels should include registration holes or fiducials that the drilling machines can use for alignment. Place fiducials on multiple layers if possible, not just the outer layers.

Panelization layouts should also consider the placement of vias near the edge of the panel or near breakaway tabs. Vias in these areas may be more susceptible to accuracy errors due to vibrations or movement during depaneling.

Material Stability and Repeatability

The consistency of the dielectric material thicknesses is critical for maintaining drilled depth accuracy across the entire panel.

FR-4 and other organic dielectrics can have thickness variations due to manufacturing tolerances, humidity absorption, or thermal expansion. These variations can stack up across larger panels.

Glass-reinforced materials like FR-4 may also have a slightly inconsistent glass weave pattern that affects the local dielectric thickness. For high-reliability applications, consider using spread-weave glass or non-glass reinforced dielectrics for improved consistency.

Thermally stable materials like polyimide or PTFE have less thickness variation than FR-4. However, they may require specialized drilling parameters and more conservative depth margins.

Drill Hit and Breakout

When drilling into a copper layer, there is a risk of drill hit and breakout if the drilling depth is too shallow. Drill hit can cause copper burrs or lifted pads that affect reliability.

To minimize drill breakout, use a depth margin of at least 4-5 mils below the target layer. For high-aspect ratio vias or thicker copper layers, a larger depth margin of 6-8 mils may be necessary.

The panelization layout should also consider the proximity of vias to the edge of the PCB or breakaway tabs. Vias near the edge may be more prone to drill hit or breakout during depaneling.

FAQ

What are the typical aspect ratio limitations for controlled depth drilling?

In general, the maximum aspect ratio for controlled depth drilling is around 10:1 (hole depth to diameter). For example, a 6 mil diameter via could be drilled up to 60 mils deep.

Higher aspect ratios up to 20:1 are possible with advanced drilling techniques like peck drilling or high-speed spindles. However, these may incur additional cost and increase the risk of inaccuracies.

How small of a via diameter can be back-drilled?

Typical back-drilling processes can handle minimum hole diameters of around 8-10 mils. Smaller holes may be possible with specialized equipment and drill bits, but the risk of inaccuracies or breakout increases.

For high-density designs with small via sizes, an alternative to back-drilling is to use blind or buried vias to avoid stubs altogether.

What is the typical turnaround time for PCBs with controlled depth drilling?

Controlled depth drilling and back-drilling are specialized processes that may add additional time to the PCB fabrication cycle. Expect an additional 2-3 days for CDD processing, and 3-5 days for back-drilling.

The exact turnaround time will depend on the complexity of the PCB stackup, number of drilling steps required, and the manufacturer’s capabilities.

Can controlled depth drilling be used with HDI PCBs?

Yes, controlled depth drilling is commonly used in HDI PCB designs to create blind and buried vias for high-density interconnects.

HDI designs often use a combination of laser-drilled microvias and mechanical CDD to create complex via structures. The microvias are typically drilled first, followed by the larger mechanical CDD holes.

How much additional cost does controlled depth drilling add to the PCB?

The cost impact of controlled depth drilling depends on the complexity of the stackup and the number of drilling steps required. In general, expect a 20-30% cost adder for CDD compared to traditional through-hole drilling.

Back-drilling can add an additional 10-20% cost adder on top of the base CDD cost, due to the extra processing steps and equipment required.

However, the total cost impact may be outweighed by the performance and reliability improvements offered by controlled depth drilling and back-drilling, especially for high-speed or high-density designs. As always, consult with your PCB fabricator for specific pricing and design trade-offs.

Conclusion

Controlled depth drilling and back-drilling are powerful techniques for optimizing PCB stackups and improving signal integrity in high-speed designs. By carefully configuring the drilling spans and depths, designers can create efficient blind and buried via structures that minimize stubs and reflections.

However, successful implementation of CDD and back-drilling requires close collaboration between the PCB designer and fabricator. Detailed stackup planning, accurate drilling instructions, and consideration for panelization effects are all critical for achieving the desired results.

With the right design approach and manufacturing controls, controlled depth drilling and back-drilling can help unlock the full potential of today’s advanced PCB technologies.